Summary:
In a groundbreaking achievement, a research team at Peking University has successfully developed a ferroelectric transistor with a physical gate length of just 1 nanometer, consuming an unprecedentedly low power of 0.45 fJ/Ξm. This innovation paves the way for the creation of high-performance, energy-efficient AI chips and sub-1-nanometer node chips.
Nanogate Ferroelectric Transistor Structure ð
The Peking University team, led by Qiu Chenguang and Peng Lianmao, has introduced a novel "nanogate ultra-low-power ferroelectric transistor" architecture. By ingeniously engineering the device structure of ferroelectric memory and introducing a nanogate-induced electric field concentration effect, the researchers have developed a ferroelectric transistor capable of operating at an ultralow voltage of just 0.6V.
Ferroelectric Transistors: A Promising Memory Technology ðĄ
Ferroelectric transistors store data through polarization switching in ferroelectric materials, which are regarded as one of the most promising semiconductor memory technologies in the post-Moore era. They hold strong potential for enabling non-volatile computing-in-memory architectures, effectively integrating storage and high-speed computation.
Overcoming the Voltage Barrier â ïļ
Conventional ferroelectric transistors have long been constrained by the intrinsic coercive voltage limits of planar ferroelectric materials. The Peking University team's innovative design creates a highly localized and intensified electric field region within the ferroelectric layer, significantly amplifying local field strength and dramatically lowering the voltage required for polarization switching.
Record-Breaking Performance â
The fabricated device delivers energy consumption as low as 0.45 fJ/Ξm, outperforming previously reported international results by an order of magnitude, with storage speeds approaching 1 nanosecond. This achievement is a significant milestone in the development of high-performance, energy-efficient AI chips and sub-1-nanometer node chips.
Future Outlook ð
The study's findings open up promising pathways for sub-1-nanometer node chips and high-compute AI chip architectures. As the physical gate length shrinks to the 1-nanometer limit, electric field convergence and enhancement become significantly stronger, underscoring the substantial potential of ferroelectric memory technologies in future sub-nanometer node chips.